Bump Bonding


The BTeV baseline pixel detector, like most other pixel systems being developed for high energy physics experiments, is based on a design relying on a hybrid approach. With this approach, the readout chip and the sensor array are developed separately, and the detector is constructed by flip-chip mating of the two. This method offers maximum flexibility in the development process, choice of fabrication technologies, and the choice of sensor materials. However, it requires the availability of a highly reliable, reasonably low cost, fine-pitch flip-chip attachment technology.

There are several bonding technologies which may be suitable for this. These include indium bumps, Pb/Sn solder bumps, fluxless solder bumps, and anisotropic conductive films (ACF) or tapes. Given the fact that we are mostly dealing with dies (for the readout chip) so far, and that our pitch is extremely fine, we chose to go with indium bumps. Even though, our recent contacts showed that Pb/Sn solder has been made to work at various places for a fine pitch, and they are a bit cheaper than indium bumps.

Both pure In and Pb/Sn solder appear to meet our requirements for providing adequate electrical and mechanical bonds at 50-microns pitch. Our task is to start qualifying vendors with facilities to provide such services to outside customers and demonstrate the quality and yield of their bump bonding services by providing bumping and bonding of a large number of dummy pixel detectors.

For this purpose, we have designed a dummy assembly module consisting of an upper and a lower array. As much as possible, the two arrays will be close to the size of the real sensor and readout chip that we will have.



  • SEM photos of indium bumps deposited at AIT on FPIX1 pixel readout chip

    FPIX1    FPIX1    Indium Bumps    Indium Bump    FPIX1    FPIX1
  • BTeV/CMS daisy-chained patterns


    Picture showing wafer layout of joint BTeV/CMS daisy-chained patterns. To be fabricated at MCNC/UNITIVE.






  • Simon Kwan's presentation on results on solder bumps at MCNC, April 11, 2000.
  • Simon Kwan's presentation on issues related to solder bumps at MCNC, April 11, 2000.
  • Picture showing flip-chip mated dummy test parts from MCNC using Eutectic solder bumps.
  • Four pictures showing the separated dummy chip and substrate that was previously flip-chip mated. The black dots are solder bumps; clear pads are non-wet UBM pads. The upper left picture shows the bumped chip. The remaining three show the same mating substrate; in each case showing non-wets in the lower left quadrant. The presence of non-wets on one quadrant of the substrate is probably due to contamination or debris on the substrate.
  • Selcuk Cihingir's write-up of his talk given in Florence, June 28, 2000



  • Pictures (including some not listed here)
  • Presentations and Documents


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    Last Update 12/13/00
    By David Christian
    Send questions to swalk@fnal.gov