PPT Slide

ti_g

to_adv

to_c

(from chip)

Rising edge is 45 ns after to_adv rising edge;

trailing edge is 40 ns after trailing edge of ti_g.

1 MHz 75% duty factor clock allows 750 ns for data to

settle before it is latched.

clr

ck_b

(“BCO clock”)

FPIX0 Readout Sequence

for 1999 beam test.